If the data acquisition access and/or release times of a peripheral device are not faster than the release time allowed for by the microprocessor, the two devices may operate in conflict with each other during data access operations resulting in acquisition conflicts producing spurious data signals on the data bus. This release time is the time interval between the completion of a data transfer and the release of the data bus by the peripheral device. To prevent occurrences of these data acquisition conflicts within the microprocessor system, peripheral device selection is normally limited to devices having substantially faster access and release times than the microprocessor. Frequently, however it is desirable to use a microprocessor with a slow peripheral device such as a memory or I/O device having longer access and/or release times than directly compatable with the microprocessor, since these slower peripheral devices are normally cheaper than fast ones.
In order to avoid data acquisition access conflicts caused by the longer access time of the slower peripheral device, the WAIT state facility of the microprocessor is frequently used. When the microprocessor addresses the slow memory or I/O device, external logic circuitry responds to the particular address and applies a signal to the microprocessor to add a WAIT state to the data acquisition cycle.
The WAIT state of a microprocessor is a period of time in which the normal processing of clock cycles is inhibited in response to a signal input to the microprocessor. Entry into the WAIT state extends the duration of time available for data access and synchronization with the slow peripheral device. While utilization of the WAIT state increases the allowable access time for slow peripheral devices, it does not increase the allowable release time for the slow peripheral device.